When a Quantum Computer Learns to Avoid Its Worst Qubits

One unreliable qubit can compromise the statistics of a much larger quantum processor. The useful question is not whether engineers can manufacture a perfect chip, but whether quantum error correction can still work when the chip is demonstrably imperfect.

On 8 October 2026, Campbell K. McLauchlan and collaborators released a preprint describing quantum memory, logical measurements and lattice-surgery experiments on IBM's 156-qubit heavy-hexagonal superconducting processor, ibm_boston. Instead of assuming identical components, the researchers changed their error-correction schedule to avoid two particularly troublesome sites, supplied their decoder with circuit-specific noise measurements and filtered runs likely to contain leakage. They report relative reductions of 32.3% and 35.2% in fitted logical error per round in Z and X memory, and improvements of up to 56% in a separate stability benchmark. [1]

These are substantial results, but the qualifiers matter. The percentages do not mean that every gate became 35% more accurate, that 156 logical qubits were constructed, or that the highest reported Bell fidelity was obtained on every attempt. The contribution is more architectural: the code, measurement circuit and decoder can be adapted to the actual device rather than a pristine theoretical lattice.

Why a good average gate fidelity is not enough

Quantum error correction distributes logical information across physical qubits. Rather than reading out the encoded state directly, an experiment repeatedly measures parity checks that reveal information about errors. In a stabilizer code, the ideal encoded state is a simultaneous positive eigenstate of a commuting family of operators. A negative check outcome can indicate an error without revealing the protected logical amplitude.

For a stabilizer group $\mathcal{S}$, the ideal code space is

Real devices rarely obey the homogeneous noise models used in introductory examples. Couplers have different calibration errors, qubits relax and dephase at different rates, and measurement quality drifts. Logical failure depends not merely on the mean physical error but on where faults occur and whether they combine into undetectable chains. A few severe outliers can dominate performance.

The studied Heron device has median two-qubit gate fidelity near 99.7%, but the paper reports qubits and couplers whose noise can be one or two orders of magnitude worse than typical components. The weakest regions cluster around physical sites 46 and 85. Those are locations on the processor, not logical qubit identifiers. A chip-wide average hides the spatial information most relevant to designing a protective code. [1]

A dynamic code for sparse heavy-hex connectivity

The heavy-hex graph is sparsely connected: not every data qubit has direct links to all the ancillas needed for a textbook square-grid check. Routing and flag operations must therefore be scheduled carefully. The authors use a dynamic compass code, whose checks follow a four-step sequence. In their implementation, X-type gauge measurements act on four data qubits and Z-type measurements act on two. Steps one and three measure X checks; the intervening steps measure complementary subsets of Z checks.

Successive gauge measurements need not all commute. Consequently, the instantaneous stabilizer group changes during the sequence. The code protects information through the periodic measurement history, not by requiring a fixed set of checks to be measured simultaneously. Schematically, the measurement schedule obeys

This equation specifies periodicity, not the complete gauge algebra. It nevertheless identifies a useful freedom: checks and detector relations can be reorganized in time around unavailable hardware. The seven-by-seven memory patch spans much of the chip and cannot simply be relocated away from all weak components. Instead, the schedule itself must change.

What it means to exclude a defective qubit

Defect exclusion is not merely a decoder assigning a lower probability to an unreliable measurement. The quantum circuit avoids using selected physical qubits and neighboring couplers. Affected gauge checks are shortened or combined, and the dynamic schedule is redesigned so that useful low-weight superstabilizer information can still be recovered. This is an intervention in the circuit before the classical decoder sees a syndrome.

A schematic stabilizer combination has the form

The actual dynamic protocol requires compatible checks and appropriate timing; the formula illustrates parity combination rather than reproducing the full experiment. Its engineering significance is that avoiding a bad component must not introduce an even more damaging, high-weight measurement circuit. More gates and longer idling periods create new fault locations.

Exclusion also has a price. In the studied seven-by-seven memory patch, removing both problematic regions reduces the effective code distances from seven to five in both bases. This makes the outcome counterintuitive: a nominally weaker adapted code performs better than the larger unadapted circuit on the same heterogeneous hardware. The authors compare exclusion of site 46, site 85 and both sites under several decoders; excluding both provides the best memory performance in that comparison. Excluding an ordinary, non-defective location instead worsens performance, an important control against the idea that simply shrinking a code explains the gain. [1]

Noise-informed decoding is a separate intervention

Once a syndrome is measured, the decoder must infer which error history most plausibly produced it. A simplified Bayesian statement is

Here $E$ denotes an error history and $s$ the observed syndrome. A generic model of physical error rates can rank histories incorrectly when the circuit has highly localized or simultaneous-operation faults. The researchers compare priors derived from IBM's reported calibrations with priors informed by averaged circuit eigenvalue sampling, or ACES. ACES characterizes noise specific to circuit layers and can capture differences caused by concurrently executed gates.

The experiment uses BeliefMatching, which combines belief propagation with matching-based decoding. ACES-informed decoding improves the logical error estimates, but it does not remove the advantage of physically avoiding the defective regions. On the June 1 dataset, ACES plus exclusion, before leakage filtering, reduces the fitted logical error per round by 23.2% in Z memory and 18.0% in X memory relative to the reported-noise baseline. [1]

This distinction has a practical consequence. A better decoder cannot necessarily compensate for a component that repeatedly contaminates neighboring checks. Conversely, avoiding too many components reduces code distance. The optimization must balance device topology, calibration, circuit depth and classical inference rather than treating those as unrelated engineering departments.

How the memory numbers are obtained

The authors prepare encoded basis states, perform repeated syndrome extraction, and measure a final logical observable. They fit the logical failure probability over rounds one through thirty to

The parameter $A$ captures preparation and readout contrast; $\tau$ is the fitted decay scale in measurement rounds. The derived $\epsilon_L$ is a logical error probability per round, not a universal gate infidelity. The data average over both prepared states in each basis. For each point the experiment aggregates four runs of 2,048 shots. [1]

Using reported-noise decoding, the fitted error per round is 6.07% in Z memory and 3.95% in X memory. Combining ACES, exclusion of both weak regions and leakage post-selection gives 4.11% and 2.56%. The relative reductions are approximately $(6.07-4.11)/6.07=32.3\%$ and $(3.95-2.56)/3.95=35.2\%$. These are configuration comparisons within a specific experiment, not predictions of universal improvements on other chips.

For context, the authors also report best unfiltered memory results of 4.4% and 2.9% per round, measured on a different day. Those values should not be compared directly with filtered numbers as if the calibration conditions were identical. The paper explicitly documents day-to-day device variation.

When a larger code is worse

Under simplified independent-noise assumptions, increasing code distance below threshold should suppress logical errors. A common scaling intuition is

Here $d$ is code distance, $p$ a characteristic physical error rate and $p_{\mathrm{th}}$ a threshold. This is not a fit to the heavy-hex measurements: it omits heterogeneous noise, leakage and correlated faults. It clarifies why the experiment is interesting. Removing components lowers distance, which ordinarily sounds counterproductive.

The team compares the seven-by-seven memory patch with nine five-by-five patches spanning different parts of its footprint. After excluding the defective regions, the larger patch meets or exceeds the average smaller-patch performance in both bases. A code that covers more hardware can be inferior if its added components are exceptionally unreliable. Code distance alone is therefore an incomplete experimental benchmark. One must specify the actual circuit, its physical placement and the noise landscape.

Leakage is not an ordinary bit flip

A transmon is not a perfect two-level system. The computational states $|0\rangle$ and $|1\rangle$ coexist with higher excited levels, including $|2\rangle$. A Pauli error remains within the intended computational subspace; leakage leaves it. Leaked population can persist through subsequent operations, creating temporal correlations that a simple independent-Pauli model cannot represent.

The researchers analyze analog in-phase and quadrature measurement signals, known as IQ data. They calibrate distributions for the first three levels and estimate the probability of leakage in individual runs. For the memory analysis, a shot is discarded if a measurement indicates at least 90% leakage probability. Among retained shots, the inferred probabilities $p_0$ and $p_1$ determine the binary measurement result.

Post-selection can make accepted data cleaner without repairing rejected runs. Consequently, conditional logical fidelity must not be confused with throughput or deterministic reliability. A scalable architecture must account for the probability of acceptance, reset time, extra measurements and whether an unsuccessful preparation can be detected before an expensive logical operation begins.

Stability: testing reliable logical measurements

A memory benchmark asks whether an encoded state survives repeated correction. A stability experiment asks whether a product of measured checks, ideally known to have fixed parity, remains inferable across many rounds. It tests a primitive needed for lattice surgery and logical Clifford operations. The authors use a five-by-five patch and sixteen check measurements per round, with defect exclusion around site 85. [1]

Without defect mitigation, the observed stability performance improves initially but plateaus after roughly twelve rounds. With the adapted circuit and leakage filtering, suppression continues through thirty rounds, and the failure probability improves by up to 56% at that point relative to the tested baseline. The paper reports a lowest stability failure probability of 15.3%. This remains a significant error rate; it is not evidence of an essentially perfect logical operation. [1]

Pauli-noise simulations in the study do not reproduce the observed plateau, which the authors associate with leakage. This is a useful warning about extrapolating simplified simulations. A noise model can match short circuits and still miss persistent, time-correlated mechanisms that dominate longer experiments. The stability analysis uses a leakage threshold of 0.7, not the 0.9 threshold used in the memory comparison.

Does soft measurement information always help?

Analog readout contains more than a hard zero-or-one label. A soft decoder can retain the confidence of each measurement rather than discarding it at thresholding. The study constructs a measurement-error prior from calibrated computational-state probabilities:

The denominator conditions on computational-subspace outcomes. An ambiguous signal gives a larger error prior than a clearly separated one. The same IQ data can also help flag leakage, but those are different uses of the information.

The reported interaction is subtle. Soft information improves stability decoding when the decoder uses reported calibration noise. When ACES information is already supplied, the extra gain is negligible in this measured regime. This does not establish that soft decoding is generally unnecessary. It suggests that richer noise characterization and richer measurement signals can sometimes compensate for overlapping deficiencies in a simpler model. Future experiments should test whether that tradeoff survives changes in drift, leakage, decoder family and circuit geometry. [1]

Lattice surgery joins two encoded patches

Quantum computing needs more than protected idle memory. Logical qubits must interact without exposing their amplitudes to destructive measurement. Lattice surgery merges and splits neighboring code patches to measure joint logical observables using local physical checks. The authors implement experiments with pairs of three-by-three and four-by-three patches positioned in relatively well-behaved regions of the chip. Their targets include logical Bell states and, in supplementary experiments, teleportation. [1]

The ideal logical Bell state is

Its ideal XX and ZZ logical correlators are both positive one. The experimental X correlator includes a surgery outcome $m_X$. Because the setup cannot measure logical YY fault-tolerantly, the researchers report bounds rather than full two-logical-qubit state tomography. Defining $C_X=\langle m_X\bar X_1\bar X_2\rangle$ and $C_Z=\langle\bar Z_1\bar Z_2\rangle$, their Bell-fidelity bounds are

Five surgery rounds are followed by a split, another syndrome-extraction round and logical readout. This is a substantive demonstration of a logical primitive, but it does not establish a complete universal fault-tolerant gate set or an indefinitely operating error-correction system.

Why 97.6% fidelity does not mean 97.6% of attempts succeed

For the three-by-three surgery experiment, the unfiltered logical Bell fidelity lies between 58.6% and 73.5%. Preparation-stage filters that exclude likely leakage and failed code-space preparation raise the interval to 77.3%–84.5%. Additional logical-gap post-selection raises the lower bound above 97.6%, with a reported 27% yield among shots that already passed preselection. [1]

The yield qualifier is essential. The 27% is conditional on earlier filters; it is not the fraction of all raw attempts that produce a 97.6%-fidelity Bell state. The rejected runs were not necessarily corrected. For the four-by-three experiment, a different filter based on belief-propagation convergence gives a 95.8%–97.5% interval at 9.64% yield under its stated conditions.

Preselection and post-selection are operationally different. A preparation check can potentially be repeated before an expensive gate begins. Discarding the result after the gate has finished can be far more costly. Practical value therefore depends on heralding, reset time, accepted-shot throughput and the resources required to retry failed preparations.

What the result does and does not establish

The experiment supports a precise conclusion: on a heterogeneous superconducting processor, defect-aware measurement scheduling, circuit-specific noise models and leakage-aware filtering can jointly improve error-corrected memory and logical-measurement primitives. The memory experiments span a large fraction of the 156-qubit device; the lattice-surgery demonstrations use smaller paired code patches. The distinction is important. A 156-physical-qubit machine is not a 156-logical-qubit machine.

Four limitations are especially relevant. Defect exclusion sacrifices effective distance and cannot be extended indefinitely to chips with many missing components. Measured improvements depend on device calibration and collection date. The strongest Bell-fidelity bounds rely on conditioning and must be accompanied by yield. Finally, this work does not demonstrate a long universal algorithm with indefinitely repeated online decoding and active logical feedback. The authors identify active leakage removal, improved device homogeneity, better decoding and further logical operations as open engineering tasks. [1]

One natural next step is to treat the architecture as a joint optimization. Let $G$ be the connectivity graph, $D$ the excluded components, $\mathcal M$ a permitted measurement schedule and $\mathcal D$ a decoder. A schematic objective is

This expression is an editorial synthesis, not an optimization solved in the paper. The cost term would penalize lost distance, extra circuit depth, calibration time and rejected shots. The formulation is useful because it forces hardware topology, code design and classical inference into one engineering decision.

The larger lesson

Quantum error correction is sometimes presented as a contest to make physical error rates smaller. This study demonstrates why that picture is incomplete. A real code has geometry, time-dependent measurements, a decoder and a physical substrate. Their interaction determines whether adding qubits helps or hurts. By adapting the code to the device, rather than demanding that the device impersonate an ideal lattice, the researchers recover performance from identifiable weak spots.

The outcome is not a completed fault-tolerant quantum computer. It is a concrete indication that useful fault tolerance will require more than an elegant code or an impressive chip in isolation. It will require a continuing agreement between the physics of the machine and the logic of the information it protects.

Primary source and image rights

[1] Campbell K. McLauchlan, Georgia M. Nixon, Julien M. Drouet, Xanda C. Kolesnikow, Seok-Hyung Lee, James Raftery, Karthik Siva, Stephen D. Bartlett, Benjamin J. Brown and Robin Harper, Error-Corrected Memory and Logic on a Heavy-Hex Superconducting-Qubit Processor, arXiv:2610.11658v1, submitted 8 October 2026. Primary abstract and version history; full paper and figure captions. This is a preprint; no claim of journal peer review is made.

[2] Creative Commons Attribution 4.0 International. The seven in-article figures and separate cover graphic are authentic assets from the primary paper. Credits and source links appear with each figure. Selected original panels are noted; no AI-generated imagery is used.